1. Field of the Invention
The present invention relates to a signal transmission system for transmitting a signal between a plurality of semiconductor integrated circuit devices that operate under different power supply voltages.
2. Description of the Related Art
There has heretofore been a system which is required to transmit a signal between semiconductor integrated circuit devices that operate under different power supply voltages. FIG. 1 shows a conventional arrangement of such a system. The system shown in FIG. 1 transmits a single-ended signal between a 1.8-V semiconductor integrated circuit device (LSI 1) and a 1.5-V semiconductor integrated circuit device (LSI 3). A voltage converter LSI (LSI 2) for converting voltages is provided between the 1.8-V semiconductor integrated circuit device and the 1.5-V semiconductor integrated circuit device for relaying a signal to be sent and received between LSI 1 and LSI 3. LSI 1 and LSI 2 are interconnected by a transmission line having characteristic impedance Z01, and LSI 2 and LSI 3 are interconnected by a transmission line having characteristic impedance Z02. Specific examples of the voltage converter LSI for converting voltages are described in Japanese laid-open patent publication No. 8-288828 and Japanese laid-open patent publication No. 11-27134.
FIG. 2 shows another conventional system which is required to transmit a signal between semiconductor integrated circuit devices that operate under different power supply voltages. The system shown in FIG. 2 transmits a single-ended signal between a 1.5-V semiconductor integrated circuit device (hereinafter also referred to as “LSI”) and 1.2-V LSI. The 1.2-V LSI comprises a receiver (having an oxide film or the like formed to a thickness capable of withstanding 1.5 V) operable by a 1.5-V power supply and an internal circuit operable under 1.2 V. By being supplied with both power supply voltages of 1.5 V and 1.2 V, the 1.2-V LSI is allowed to transmit a signal to and from the 1.5-V LSI. While FIG. 2 illustrates an example wherein a signal is transmitted from the 1.5-V LSI to the 1.2-V LSI, the actual signal transmission system is capable of bidirectionally sending and receiving signals.
FIG. 3 shows a specific signal transmission system having uniform power supply voltages to be supplied to components required to perform the signal transmission shown in FIG. 2. FIG. 3(a) shows an arrangement for transmitting a single-ended signal from 1.5-V LSI (DRAM) to 1.2-V LSI having a driver and a receiver which are supplied with 1.5 V, and FIG. 3(b) shows an arrangement for performing a reversed signal transmission. The LSIs are mounted on respective PCBs (Printed Circuit Boards) and interconnected by a transmission line having a characteristic impedance Z0 of 50 ?. The driver for sending a signal comprises a pMOS and an nMOS transistors which are pushpull-connected (push-pull configuration), and has an on-resistance of 20 ?. The receiver for receiving a signal is terminated with CTT (Center Tapped Termination, which may be referred to as Thevenin termination). The value of the terminating resistor of the CTT circuit is equalized to the characteristic impedance Z0 for impedance matching. The value of the terminating resistor of the CTT circuit is the same as the value obtained when the illustrated upper and lower resistors of the CTT circuit are connected parallel to each other. If the values of the power supply voltages (VDDQ) to be supplied to the driver and the receiver that are used for signal transmission are thus uniformized, then the system is capable of sending and receiving a signal without fail.
FIG. 4 shows an arrangement wherein semiconductor integrated circuit devices, each having a driver and a receiver, which are operable under different power supply voltages are connected in series with each other for bidirectionally transmitting a single-ended signal. Although there appears to be no system which would employ the arrangement shown in FIG. 4, the illustrated arrangement is used to assist in understanding the present invention. In FIG. 4, squares represent switches which are turned off when a signal is to be sent. In FIG. 4, the driver comprises a pMOS and an nMOS transistors which are push-pull-connected, and the receiver is terminated with CTT.
With this arrangement, since different power supply voltages (VDDQ) are supplied to the two LSIs for sending and receiving a signal, different reference voltages Vref are supplied to the respective receivers as threshold values for determining input voltages.
FIG. 5 shows a specific arrangement of the signal transmission system shown in FIG. 4. In FIG. 5, as with FIG. 3, the driver comprises a PMOS and an nMOS transistors which are push-pull-connected, the receiver is terminated with CTT, the driver has an on-resistance of 20 ?, the transmission line has a characteristic impedance of 50 ?, and the terminating resistor of the receiver has a value of 50 ?. FIG. 5(a) shows an equivalent circuit for sending a single-ended signal from the 1.5-V LSI, and FIG. 5(b) shows an equivalent circuit for sending a single-ended signal from the 1.2-V LSI.
As shown in FIG. 5(a), for sending a signal from the 1.5-V LSI, the output signal has a high level VOH of 1.24 V and a low level VOL of 0.17 V, and the reference voltage Vref set to an intermediate value between VOH and VOL is 0.71 V. Therefore, the reference voltage Vref for receiving the signal with the 1.2-V LSI is 0.71V.
As shown in FIG. 5(b), for sending a signal from the 1.2-V LSI, the output signal has a high level VOH of 1.07 V and a low level VOL of 0.21 V, and the reference voltage Vref set to an intermediate value between VOH and VOL is 0.64 V. Therefore, the reference voltage Vref for receiving the signal with the 1.5-V LSI is 0.64V.
FIG. 6 shows an arrangement wherein semiconductor integrated circuit devices (1.5-V LSI and 1.2-V LSI 3), each having a driver and a receiver, which are operable under different power supply voltages are connected in series with each other for bidirectionally transmitting a single-ended signal. Although there appears to be no system which would employ the arrangement shown in FIG. 6, the illustrated arrangement is used to assist in understanding the present invention. In FIG. 6, squares represent switches which are turned off when a signal is to be sent. In FIG. 6, the driver comprises a pMOS and an nMOS transistors which are push-pull-connected, and the receiver is of an arrangement (CTT-terminated circuit) having an input terminal pulled up to a terminating voltage VTT. FIG. 6 also shows an arrangement having 1.2-V LSI operable under a 1.2-V power supply for transmitting a signal between the 1.2-V LSI 3 and the 1.2-V LSI.
Even with the above arrangement, since the power supply voltages (VDDQ) supplied to the 1.5-V LSI and the 1.2-V LSI 3 for sending and receiving a signal are different from each other, reference voltages Vref as threshold values for determining an input voltage and values of VTT, which are supplied to the receiver, are different from each other.
FIG. 7 shows a specific arrangement of the signal transmission system shown in FIG. 6. In FIG. 7, the driver comprises a pMOS and an nMOS transistors which are push-pull-connected, the receiver is pulled up to VTT by a terminating resistor, the driver has an on-resistance of 20 ?, the transmission line has a characteristic impedance of 40 ?, and the terminating resistor of the receiver has a value of 40 ?. FIG. 7(a) shows an equivalent circuit for transmitting a single-ended signal from the 1.5-V LSI, and FIG. 7(b) shows an equivalent circuit for transmitting a single-ended signal from the 1.2-V LSI 3.
As shown in FIG. 7(a), for sending a signal from the 1.5-V LSI, the output signal has a high level VOH of 1.25 V and a low level VOL of 0.25 V, and the reference voltage Vref set to an intermediate value between VOH and VOL is 0.75 V. Therefore, the reference voltage Vref for receiving the signal with the 1.2-V LSI is 0.75V.
As shown in FIG. 7(b), for sending a signal from the 1.2-V LSI 3, the output signal has a high level VOH of 1.00 V and a low level VOL of 0.20 V, and the reference voltage Vref set to an intermediate value between VOH and VOL is 0.60 V. Therefore, the reference voltage Vref for receiving the signal with the 1.5-V LSI is 0.60V.
The foregoing signal transmission systems suffer the following problems:
First, the arrangement having the voltage converter LSI as shown in FIG. 1 is problematic in that since the propagation speed of signals is reduced by the voltage converter LSI, the system performance is lowered. Furthermore, the cost of the system increases because the number of parts used is increased by using the voltage converter LSI.
The arrangement wherein the 1.5-V power supply is supplied to the 1.2-V LSI shown in FIG. 2 is problematic in that the LSI fabrication process tends to be complex because of the need for a process for making the oxide film partially thick. Another problem is that terminals are required to supply the 1.5-V power supply, and the cost of the 1.2-V LSI is increased due to an increase in the LSI package size and the number of terminals.
The arrangement as shown in FIG. 4, wherein the semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected for bidirectionally transmitting a signal, requires two types of reference voltages Vref. Therefore, relatively expensive reference voltage generating circuits are needed, and two types of interconnection patterns for reference voltages of different potentials are required, resulting in an increased number of layers in the PCB and hence an increased system cost. Though two types of reference voltages are required, if a reference voltage Vref that is actually supplied is limited to either one of them, then the following problem arises:
In the example shown in FIG. 5, 0.71 V and 0.64 V are used as the reference voltages Vref. If the reference voltage Vref supplied to the two LSIs is set to 0.64 V, for example, then the 1.5-V LSI is not affected, but since the reference voltage Vref for the 1.2-V LSI is lowered, the 1.2-V LSI is affected as shown in FIG. 8.
Specifically, when the received signal goes high, the input circuit (receiver) responds more quickly than when the reference voltage Vref of 0.71 V is supplied. However, when the input signal goes low, the input circuit (receiver) responds more slowly than when the reference voltage Vref of 0.71 V is supplied, resulting in a timing skew in the input circuit.
If the received signal has a rise time tR and a fall time tF, both of about 250 ps, then the timing skew is 33 ps. This value corresponds to 5.2% of an eye window (bit time)=625 ps of a signal which has a transmission rate of 1.6 Gbps, and cannot be ignored. If the timing skew increases due to a reduction in the reference voltage Vref, then the possibility of an error becomes higher.
The other arrangement as shown in FIG. 6, wherein the semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected for bidirectionally transmitting a signal, also requires two types of reference voltages Vref and terminating voltages VTT. Therefore, two types of reference voltage generating circuits and VTT generating circuits are needed, and two types of interconnection patterns for reference voltages having different potentials and terminating voltages VTT are needed. As there is a possibility for an increased number of PCB layers, the system cost tends to rise.
Though there are two types of reference voltages and terminating voltages VTT, if a reference voltage Vref and a terminating voltage VTT that are actually supplied are limited to either one of them, then the same problem as with FIG. 5 arises.